1. Field of the Invention
The present invention relates to a monolithic ceramic capacitor, and in particular, to a monolithic ceramic capacitor having a plurality of terminals arranged to reduce equivalent series inductance (ESL).
2. Description of the Related Art
In a power supply circuit, when a voltage variation in a power supply line is increased by impedance that is present in the power supply line or a ground, the operation of circuits to be driven becomes unstable, interference between the circuits occurs due to the power supply circuit, or oscillation occurs. Consequently, a decoupling capacitor is usually connected between the power supply line and the ground. The decoupling capacitor decreases alternating impedance between the power supply line and the ground, thereby suppressing the variations in the power supply voltage and interference between the circuits.
Recently, in communication equipment such as a cell phone and information processing equipment such as a personal computer, as the speed of signals has been increased in order to process a large amount of information, the clock frequency of an IC used is also increased. Accordingly, noise that primarily includes harmonic wave components is readily generated. Therefore, it is necessary to provide a stronger decoupling in an IC power supply circuit.
In order to increase the decoupling effect, it is effective to use a decoupling capacitor having an excellent impedance-frequency characteristic. An example of such a decoupling capacitor is a monolithic ceramic capacitor. Because of its low ESL, the monolithic ceramic capacitor has an excellent noise-absorbing effect over a wide frequency band as compared to an electrolytic capacitor. As a monolithic ceramic capacitor suitable for such a decoupling, for example, Japanese Unexamined Patent Application Publication No. 11-144996 discloses a monolithic ceramic capacitor having a plurality of terminals for the purpose of further reducing ESL.
Stabilization of a power supply circuit also significantly depends on equivalent series resistance (ESR) of the capacitor. In the above-described monolithic ceramic capacitor with a decreased ESL, as the number of terminals increases, the number of leading portions of inner electrodes is also increased, resulting in a significant decrease in ESR. Accordingly, a power supply circuit including such a monolithic ceramic capacitor is disadvantageous in that the stability is not satisfactory. The monolithic ceramic capacitor in which ESL is decreased by the above-described structure has an extremely low ESR. Accordingly, when resonance is induced by inductance in the peripheral circuit, the power supply voltage markedly drops or a damped oscillation, such as ringing, easily occurs.
Consequently, for example, Japanese Unexamined Patent Application Publication No. 2001-284170 discloses a monolithic ceramic capacitor in which a marked decrease in ESR is prevented while ESL is decreased.
The monolithic ceramic capacitor described in Japanese Unexamined Patent Application Publication No. 2001-284170 includes a ceramic laminate having a plurality of laminated ceramic layers. In the monolithic ceramic capacitor, a plurality of first outer electrodes to which a first polarity is assigned and a plurality of second outer electrodes to which a second polarity is assigned are provided on side surfaces of the ceramic laminate so that the first outer electrodes and the second outer electrodes are alternately arranged. A plurality of first inner electrodes and a plurality of second inner electrodes are provided inside the ceramic laminate. Each of the first inner electrodes is electrically connected to only one of the first outer electrodes. Each of the second inner electrodes is electrically connected to only one of the second outer electrodes. In the monolithic ceramic capacitor having this structure, the ESR of the monolithic ceramic capacitor is increased because the number of leading portions of each inner electrode for electrically connecting to one of the outer electrodes is only one.
However, the monolithic ceramic capacitor described in Japanese Unexamined Patent Application Publication No. 2001-284170 has the following problems.
First, the process for determining the total capacitance of the monolithic ceramic capacitor is complex. More specifically, the total capacitance of the monolithic ceramic capacitor must be determined by adding capacitances measured between adjacent outer electrodes together. Alternatively, the total capacitance of the monolithic ceramic capacitor must be measured while all the outer electrodes are connected to a wiring substrate.
In addition, in a state in which the monolithic ceramic capacitor is mounted on a wiring substrate, with solder therebetween, when a solder crack or other defect is generated at a single position and the connection between the outer electrode and a conductor land is disconnected at only the single position, the capacitance in the case in which the inner electrode is connected to the disconnected outer electrode cannot be obtained. Consequently, the capacitance is substantially decreased.